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The=20 Audio Pages

 Elliott Sound = Products Class-D=20 Amplifiers 

Class D Audio Amplifiers - Theory and = Design
=A9 June=20 2005, Sergio S=E1nchez Moreno (ColdAmp)
Edited & = Additional Text by=20 Rod Elliott (ESP)
Page Created 04 June 2005

Articles Index
Main Index

Contents=20

1 -   Introduction

A completely new technology for audio amplification has been evolving = during=20 the last 15-20 years that has a clear benefit over current widespread = Class-A,=20 and AB topologies. We are talking about the so-called =93Class-D=94. = This benefit is=20 mainly its high power efficiency. Figure 1 shows typical efficiency = curves vs.=20 Output power for Class-B and Class-D designs.

The theoretical maximum efficiency of Class-D designs is 100%, and = over 90%=20 is attainable in practice. Note that this efficiency is high from very = moderate=20 power levels up to clipping, whereas the 78% maximum in Class-B is = obtained at=20 the onset of clipping. An efficiency of less than 50% is realised in = practical=20 use with music signals. The PWM amp's high power efficiency translates = into less=20 power consumption for a given output power but, more important, it = reduces=20 heatsink requirements drastically. Anyone who has built or seen a = high-powered audio amplifier has noticed that big aluminium extrusions are needed to = keep=20 the electronics relatively cool. The loading on the power transformer is = also=20 reduced by a substantial amount, allowing the use of a smaller = transformer for=20 the same power output.


Figure 1 - Efficiency Comparison for Class-D = and=20 Class-AB

These heatsinks account for an important part of the weight, cost and = size of=20 the equipment. As we go deeper in the details of this topology, we will = notice=20 that a well behaving (low distortion, full range) Class-D amplifier must = operate=20 at quite high frequencies, in the 100KHz to 1MHz range, needing very = high speed=20 power and signal devices. This has historically relegated this class to = uses=20 where full bandwidth is not required and higher distortion levels are = tolerable=20 - that is, subwoofer and industrial uses.

However, this has changed and thanks to today's faster switches, = knowledge=20 and the use of advanced feedback techniques it is possible to design = very good=20 performance Class-D amplifiers covering the whole audio band. These = feature high=20 power levels, small size and low distortion, comparable to that of good = Class-AB=20 designs. (From now on, I will refer to Class-A and AB topologies as=20 =93classical=94).


Complete 400W Full-Range Class-D Amplifier = Module=20 (Courtesy of ColdAmp)

From the DIY perspective, Class-D is rather unfortunate. Because of = the=20 extremely high switching speeds, a compact layout is essential, and SMD = (surface=20 mount devices) are a requirement to get the performance needed. The = stray=20 capacitance and inductance of conventional through-hole components is = such that=20 it is almost impossible to make a PWM amplifier using these parts. = Indeed, the=20 vast majority of all ICs used for this application are available = only in=20 surface mount, and a look at any PWM amplifier reveals that conventional = components are barely used anywhere on the board. Since SMD parts are so = hard to assemble by hand and the PCB design is so critical to final = performance, DIY=20 versions of PWM amps are very rare indeed (I don't know of any).

2 -   How Class-D Works

In classical amplifiers, at least one of the output devices (let them = be=20 bipolar transistors, MOSFETs or valves) is conducting at any given time. = No=20 problem so far, but they are also carrying a given current where there = is a=20 voltage drop between collector-emitter / drain-source etc. Since=20 P =3D V * I, they are dissipating power, and even if = there is=20 no output a small quantity of current must pass through the transistors = to avoid=20 crossover distortion, so some dissipation is present. As the output = voltage increases, for given supply rails the voltage drop across the = transistors will=20 fall, but the current increases. At saturation (clipping), VCE or VDS = will be=20 low, but current is quite high (Vout / Rspk). Conversely, at low power = levels,=20 current is small but voltage drop is large. This leads to a power = dissipation=20 curve that is not linear with output power. There is a non-zero minimum=20 dissipation (zero percent efficiency), and a point where maximum = efficiency is=20 reached ... about 78% in pure Class-B designs, 25% or less with = Class-A.

Class-D on the other hand, bases its operation in switching output = devices=20 between 2 states, namely =93on=94 and =93off=94. Before discussing the = topology specific=20 details, we can say that in the =93on=94 state, a given amount of = current flows=20 through the device, while theoretically no voltage is present from drain = to=20 source (yes, almost every Class-D will use MOSFETs), hence power = dissipation is=20 theoretically zero. In the off state, voltage will be the total supply = rails as=20 it behaves like an open-circuit, and no current will flow (that's very = close to=20 reality).

But how can our beloved audio signal be represented by an awful = square wave=20 with only two possible levels? Well, in fact it modulates some = characteristics=20 of this square wave so the information is there. Now we =93only=94 have = to=20 understand the way the modulation is done and how to restore the = amplified audio=20 signal from it. The most common modulation technique used in Class-D is = called=20 PWM (Pulse Width Modulation) - a square wave is produced that has a = fixed=20 frequency, but the time it is in the =93high=94 and =93low=94 = states is not=20 always 50%, but it varies following the incoming signal. This way, when = the=20 input signal increases, the =93high=94 state will be present for longer = than the=20 =93low=94 state, and the opposite when the signal is =93low=94. If we do = some maths, the=20 mean value of the signal in a single cycle is simply ...

T=20 being the period of the signal, that is, 1/Fsw (switching frequency).

For example, the mean value of a 50% duty cycle (both states are = present for=20 exactly the same amount of time) signal going from +50V to =9650V is: 50 = * 0.5 +=20 (- 50) * 0.5 =3D 0V. In fact, the idle (no signal) output of a Class-D = amplifier=20 is a 50% duty cycle square signal switching from the positive to the = negative=20 rail.

If we modulate the input up to the maximum, we will have a near-100% duty-cycle. Lets put 99%: Vmean =3D 50 * 0.99 + (-50) * 0.01 =3D 49V. = Conversely,=20 if the signal is lowest, we need near 0% (lets use 1%), so Vmean =3D = -49V.

PWM is usually generated by comparing the input signal with a = triangle=20 waveform as shown in Figure 2. The triangle wave defines both the input=20 amplitude for full modulation and the switching frequency

3D"Figure
Figure 2 - Basic PWM = Generation

Figure 3 shows a typical PWM signal modulated by a sine wave. Notice = that it=20 is designed so signals between =961 and 1V will produce 0% to 100% duty = cycles,=20 50% corresponding to 0V input. The 'digital' output uses standard logic = levels,=20 where 0V is a logic '0' and 5V is a logic '1'. Because of this = digitisation of=20 the signal, PWM amps are sometimes erroneously referred to as digital = amps. In=20 fact, the entire process is far more analogue than digital.

3D"Figure
Figure 3 - Aspect of a PWM modulated=20 signal

Notice that for a correct representation of the signal, the frequency = of the=20 PWM reference waveform must be much higher than that of the maximum = input=20 frequency. Following Nyquist theorem, we need at least twice that = frequency, but=20 low distortion designs use higher factors (typically 5 to 50). The PWM = signal=20 must then drive power conversion circuitry so that a high-power PWM = signal is=20 produced, switching from the +ve to =96ve supply rails (assuming a = half-bridge topology).

The spectrum of a PWM signal has a low frequency component that is a = copy of=20 the input signals spectrum, but also contains components at the = switching=20 frequency (and its harmonics) that should be removed in order to = reconstruct the=20 original modulating signal. A power low-pass filter is necessary to = achieve=20 this. Usually, a passive LC filter is used, because it is (almost) = lossless and=20 it has little or no dissipation. Although there must always be some = losses, in=20 practice these are minimal.

3 -   Topologies

There are basically two Class-D topologies - half-bridge (2 output = devices=20 are used) and full-bridge (4 output devices). Each one has its own = advantages.=20 For example, half-bridge is obviously simpler and has more flexibility = as a=20 half-bridge amplifier can be bridged as with classical topologies. If it = is not=20 correctly designed and driven, can suffer from =93bus pumping=94 = phenomena (transfer=20 current to the power supply that can make it increase its voltage = producing=20 situations dangerous to the amplifier, supply and speaker).

Full bridge requires output devices rated for half the voltage as an = half=20 bridge amplifier of the same power, but it is more complicated. Figures = 5a and=20 5b show both topologies conceptually. Obviously, many components such as = decoupling capacitors, etc are not shown.

3D"Figure
Figure 4a - Half bridge Class-D=20 topology

3D"Figure
Figure 4b - Full bridge Class-D=20 topology

Note that full bridge PWM amp needs only one supply rail - bipolar = supplies=20 are not necessary, but can still be used. When a single supply is used, = each=20 speaker lead will have =BD the Vdd voltage present. As it is connected=20 differentially, the loudspeaker doesn't see any DC if everything is well = balanced. However, this can (and does) cause problems if a speaker lead = is=20 allowed to short to chassis!

The filter may be implemented by means of a single capacitor across = the=20 loudspeaker, by a pair of caps to ground, or in some cases by both (as = shown by=20 the dotted lines connecting the caps).

For the rest of the document, we will concentrate on half-bridge = topologies,=20 although the vast majority of the ideas are also applicable to = full-bridge=20 designs.

Half bridge design

The operation of the half bridge circuit depicted in Figure 4a is as = follows=20 ...

When Q1 is on (corresponding to the positive part of the PWM cycle), = the=20 switching node (inductor input) is connected to Vdd, and current starts = to=20 increase through it. The body diode of Q2 is reverse biased. When Q2 is = on=20 (negative part of the PWM cycle), the body diode of Q1 is reverse biased = and the=20 current through Lf starts to decrease. The current waveform in Lf is = triangular=20 shaped.

Obviously, only one of the transistors must be on at any time. If for = any=20 reason both devices are enhanced simultaneously, an effective = short-circuit=20 between the rails will be produced, leading to a huge current and the=20 destruction of the MOSFETs. To prevent this, some =93dead-time=94 (a = small period=20 where both MOSFETs are off) has to be introduced.

Lf in conjunction with Cf and the speaker itself form the low pass = filter=20 that reconstructs the audio signal by averaging the switching node = voltage.

Timing is critical in all this process: any error as delays or = rise-time of=20 the MOSFETs will ultimately affect efficiency and audio quality. So all = the=20 involved components must be high-speed. Dead-time also affects = performance, and=20 it must be minimised. At the same time, the dead-time must be = sufficiently long=20 to ensure that under no circumstance both MOSFETs are on at the same = time.=20 Typical values are 5 to 100ns.

The dead-time is a critical factor for distortion performance. For = lowest=20 distortion, the dead-time must be as small as possible, but this risks=20 'shoot-through' currents, where both MOSFETs are on simultaneously. This = not=20 only increases distortion and dissipation dramatically, but will quickly = destroy=20 the output devices. If the dead-time is too great, the response of the = output=20 stage no longer follows the true PWM signal generated in the modulator, = so again distortion is increased. In this case, dissipation is not affected.

4 -   Gate Driving

To ensure fast rise/fall times of the MOSFETs, the gate driver must = provide=20 quite a high current to charge and discharge the gate capacitance during = the=20 switching interval. Typically, 20 - 50ns rise/fall times are needed, = requiring=20 more than 1A of gate current.

Note that the schematics shown use both N-channel MOSFETs. Although = some=20 designs use N and P channel complementary devices, that is IMHO = sub-optimal due=20 to the difficulty of obtaining suitable P devices and matched pairs. So = lets=20 concentrate on N-channel only half-bridges. Note that, in order to drive = a=20 MOSFET on, a voltage above Vth must be present between its gate and = source. The=20 lower MOSFET has its source connected to =96Vss, so its drive circuit = has to be=20 referred to that node instead of GND.

However, the upper MOSFET is more difficult to drive, as its source = is=20 continuously floating between +Vdd and =96Vss (minus drops due to on = resistance).=20 However, its driver must be also floating on the switching node and, = what's=20 more, for the on-state, its voltage must be several volts above +Vdd so = a=20 positive Vgs voltage is created when Q1 is on. This also implies a = voltage=20 shifting so the modulator circuit can communicate correctly with the = driver.

This is one of the major difficulties of Class-D design: gate drive. = To solve=20 the issue, several approaches are taken ...

Figure 5 (a, b & c) = depict=20 some possibilities for 'High Side' gate driving ...

3D"Figure
Figure 5a - Transformer = Coupled		 3D"Figure
Figure 5b - Discrete BJT = Driver		 3D"Figure
Figure 5c - IC = Driver

Note that circuits in figures 5b and 5c have their PWM input referred = to =96Vss=20 so may require previous level shifting of the comparator output, that = will=20 normally be referred to GND. Fig 5a will require level shifting of the = inverted=20 PWM only, as the transformer input can be referenced to GND as shown. = Many of=20 the driver ICs available now have inbuilt level shifters, and these are=20 optimised for speed. Remember that any delay introduced into the=20 switching waveform can cause distortion or simultaneous MOSFET = conduction.

We have still one problem to solve ... obtaining 12V above VS (the = switching=20 node). We can add another power supply, isolated from the main one, = which (-) is=20 connected to VS. This solution can be impractical, so other techniques = are=20 commonly used. The most widespread is a 'bootstrap' circuit. The = bootstrap=20 technique uses a charge pump built with a high speed diode and a = capacitor. The=20 output of the amplifier produces the switching pulses needed to charge = the=20 capacitor.

3D"Figure
Fig. 6 Bootstrap capacitor provides the high = side=20 driver supply voltage

This way, the only auxiliary power supply needed is 12V referenced to = =96Vss=20 that is used for powering both the low side driver and the charge pump = for the=20 high side driver. As the average current from this supply is low = (although there=20 are high current charging peaks during the switching events, they last = only=20 20-50ns, twice during a cycle, so the average is quite low, in the = 50-80mA=20 range), this supply is easily obtained from the negative rail with a = simple 12V=20 regulator (paying attention to its maximum input voltage rating, of = course).

5 -   Level Shifting

As can be seen from the previous figures, in order to excite the = MOSFET driver, the PWM signal has to be referred to =96Vss. So, as the = modulator usually=20 works from +/-5 to +/-12V, typically, a level shifting function is = needed. One=20 can choose to shift the level of the PWM signal and then generate the = inverted=20 version, or generate both outputs and invert both of them. It depends, = for=20 example, on the comparator type used (if complementary outputs are = available,=20 the decision is made).

A basic level shifting function can be performed with a single or two-transistor circuit similar to the one depicted in Figure 6 (before = the high=20 side driver). While this may work at low frequencies, it is important to = simulate the behaviour of the comparator and level shifter, as they can=20 introduce considerable delays and timing errors if not properly = designed.

It is fair to say that the level shifter is one of the most critical = parts of=20 the circuit, and this is evidenced by the wide variety of competing ICs = designed=20 for the job. Each will have advantages and disadvantages, but in all = cases the=20 complexity is far greater than may be implied by the simplified = diagrams.

6 -   Output Filter Design

The output filter is one of the most important parts of the = circuit, as the overall efficiency, reliability and audio performance depends on = it. As=20 previously stated, a LC filter is the common approach, as it is = (theoretically)=20 lossless and has a =9640dB/decade slope, allowing for a reasonable = rejection of=20 the carrier if the parameters of the filter and the switching frequency = itself=20 are properly designed.

The first thing to do is to design the transfer function for the = filter.=20 Usually, a Butterworth or similar frequency response is chosen, with a = cutoff=20 frequency slightly above the audio band (30-60KHz). Have in mind that = one of the=20 design parameters is the termination load, that is, the speaker = impedance.=20 Usually, a typical 4 or 8 ohm resistor is assumed, but that would = produce=20 variations in the measured frequency response in presence of different = speakers.=20 That must be compensated for by means of proper feedback network design. = Some=20 manufacturers simply leave it that way so the response is strongly = dependent on=20 the load. Surely a non-desirable thing.

The design can be done mathematically or simply use one of the many = software=20 programs available that aid in the design of LC filters. After that, a=20 simulation is always useful. Figure 7 shows a typical LC filter for = Class-D=20 amplifiers and its typical frequency response.

3D"Figure
Figure 7 - Frequency Response of a Typical = Class-D LC=20 2nd Order Filter

This simple filter has a =963dB cutoff frequency of 39KHz (with 4 ohm = load),=20 and suppresses the carrier as much as 31dB at 300KHz. For example, if = our supply=20 rails are +/-50V (enough for about 275W at 4 ohms), the residual ripple = will=20 have an amplitude of about 1Vrms.

This ripple is, obviously inaudible, and 1V RMS will dissipate only = around=20 200mW in a typical tweeter (not likely a problem, especially since the = tweeters=20 impedance will be a lot higher than 8 ohms at 300kHz). However, care = must be=20 taken as the speaker wires can become an antenna and affect other = equipment. In=20 fact, although a couple of volts RMS of ripple can seem low enough to = run your=20 speakers safely, EMI can be a concern, so the less carrier level you = have, the=20 better. For further rejection, higher order filters are used (with the = potential disadvantage of increased phase shift in the audio band), although = there are=20 other clever ways to do it, as very selective bandstop or 'notch' = filters tuned=20 to the carrier frequency (if it is fixed, and that only happens in = synchronous=20 designs as the one described).

Well designed Class-D amplifiers have a higher order filter and/or = special=20 carrier suppression sections in order to avoid problems with EMI. As can = be seen=20 in Figure 8, the response is dependent on the load, and in fact the load = is part=20 of the filter. This is one of the problems to solve in Class-D designs. = It=20 doesn't help that a loudspeaker presents a completely different = impedance to the=20 amplifier than a test load, and many PWM amps have filters that are (and = never=20 can be) correct for all practical loudspeaker loads. Again, only a = handful of good Class-D amplifiers use feedback techniques that include the output = filter=20 to compensate for impedance variations and have a nearly load = independent=20 frequency response, as well as to reduce distortion produced by = non-linearities=20 in the filter. Although passive components are thought to be = distortion-free,=20 this does not apply to ferrite or powdered iron cores that are used for = the=20 filters. These components most certainly do introduce distortion.

Now, The Filter Components ...
The output inductor has to = withstand the=20 whole load current, and also have storage capability, as in any = non-isolated=20 switching converter (Class-D half bridge design is in fact analogous to = a buck=20 converter, its reference voltage being the audio signal).

The ideal inductor (in terms of linearity) is an air-core one, but = the size=20 and number of turns required for typical Class-D operation usually makes = it=20 impractical, so a core is normally used in order to reduce turns count = and also=20 provide a confined magnetic field that reduces radiated EMI. Powder = cores or=20 equivalent materials are the common choice. It can also be done with = ferrite=20 cores, but they must have a =93gap=94 where energy is stored. Wire size = must also be=20 carefully chosen so DC losses are low (requiring thick wire) but also = skin=20 effect is reduced (AC resistance must also be low).

Inductor core shape can be a drum core, gapped ferrite RM core, or = toroidal=20 powder core, among others. Drum cores have the problem that their = magnetic field=20 is not enclosed, hence producing more radiated EMI. RM cores solve this = problem=20 but have most of the coil enclosed, so cooling problems may arise as no = airflow=20 is possible. IMHO, toroids are preferred because they feature both = closed=20 magnetic field that helps control radiated EMI, a physically open = structure that=20 allows proper cooling, and easy and economical winding, as they don't = need=20 bobbins.

3D"Drum 3D"Toroid 3D"Drum
Coil Shapes ... Drum, Toroid & RM Style = Coils and=20 Cores (Wilco & Coilcraft)

Many core manufacturers such as Micrometals or Magnetics offer their = own=20 software, very useful to design the output inductor as they help = choosing the=20 right core, wire size and geometrical parameters. The capacitor usually = falls in=20 the 200nF to 1uF range, has to be of good quality too, in order to = ensure good=20 high frequency behaviour and low losses and of course has to be rated = for the=20 whole output voltage. Usually, polypropylene capacitors are chosen. = Needless to=20 say, you cannot use electrolytics!

7 -   Feedback

As I have stated previously, timing errors can lead to increased distortion and noise. This cannot be skipped and the more precise it is = kept,=20 the better the design will perform. Anyway, open loop Class-D amplifiers = are not=20 likely to satisfy demanding specifications, so (negative) feedback is = almost=20 mandatory. There are several approaches. The most simple and common is = to take a=20 fraction of the switching signal, precondition it by means of a passive = RC low=20 pass filter and feed it back to the error amplifier.

To put it simply, the error amplifier is an opamp placed in the = signal path=20 (before the PWM comparator) that sums the input signal with the feedback = signal=20 to generate a error signal that the amps automatically minimises (this = is the=20 concept of every negative-feedback system, anyway).

3D"Figure
Figure 8 - Typical Feedback Network=20 Connections

Although good results are obtained this way, there is still a = problem: load=20 dependency, due to the speaker being an integral part of the filter, = hence=20 affecting its frequency response as shown above.

Some more advanced amplifiers take the feedback signal from the very = output,=20 trying to compensate this. This way, a constant frequency response is = obtained,=20 with the further gain that the inductor resistance contributes much less = to the=20 output impedance, so it is kept lower, hence damping factor is higher = (higher=20 speaker control). However, taking feedback after the filter is not an = easy task.=20 The LC introduces a pole and hence a phase shift that, if not properly compensated, will make the amp become unstable and, ultimately, = oscillate.=20 Feedback may be taken from both the switching node and the filter = output.=20 Although this can give very good results, it is still difficult to = maintain=20 stability because of the phase shift through the output filter.

8 -   Other topologies

Pure PWM (based on triangle generators, also called 'natural = sampling PWM') is not the only way to go in order to construct a Class-D = amplifiers.=20 Some other topologies have arisen, many of them based on = auto-oscillation, where=20 the hysteresis in the comparator and delays between the comparator and = power=20 stage can be taken into account to design a system that oscillates by = itself in=20 a somewhat controllable manner.

Although simpler, these designs have some disadvantages, IMHO. For = example,=20 the switching frequency is not fixed, but depends on the signal = amplitude. This=20 makes output notch filters ineffective, yielding higher ripple levels. = Besides,=20 when several channels are put together, the difference in switching = frequency=20 between them can produce audible beat tones that can become very = annoying. This=20 can also happen of course with synchronous design as the one described = here, but=20 there is a simple solution - use the same clock for all the = channels.

Self oscillating designs in particular have some other difficulties = like=20 start-up: special circuitry may be needed that forces the amplifier to = start=20 oscillating. Conversely, if for any reason the oscillation stops, you = could end=20 up with an 'always-on' MOSFET, and thus a large amount of DC at the = output,=20 followed almost immediately by a dead loudspeaker. Of course, these = issues can=20 be solved with proper design, but the added complexity can void the = initial=20 simplicity, thus no gain is obtained.

Low distortion in a PWM amplifier requires a very linear triangle = waveform,=20 along with a very fast and accurate comparator. At the high operating=20 frequencies needed for optimum overall performance, the opamps used need = to have=20 a wide bandwidth, extremely high slew rate, and excellent linearity. = This is=20 expensive to achieve, requiring premium devices. Some of these = constraints are=20 relieved somewhat by self oscillating designs (therefore making them = slightly=20 cheaper), but this is not an effective trade-off for the most part.

Clocked designs (fixed frequency) are not easier to make than self-oscillating or modulated switching frequency designs, but are = certainly=20 far more predictable and tend to have fewer problems overall. The = ability to=20 synchronise multiple amplifiers ensures that mutual interference is = minimised.=20 An 'advantage' claimed by the proponents of non-clocked and 'random = switching'=20 designs is that the RF energy on the speaker leads is spread over a wide = frequency range, potentially making such amplifiers more likely (or = perhaps less=20 unlikely) to pass EMI testing. From an overall perspective, this is more = likely=20 to be a hinderance than a benefit, as it is no longer possible to = optimise the filter network for maximum switching frequency rejection.

There are also PWM amps that claim to be truly 'digital', using = One-Bit=99=20 technology, or generating the PWM signal directly from the PCM data = stream.=20 Although the manufacturers of such amplifiers will naturally proclaim = their=20 superiority over all others, such self-praise should generally be = ignored.=20 Implementing feedback in a 'pure' digital design is at best difficult, = and may=20 be impossible without using a DSP (digital signal processor) or = resorting to an=20 outboard analogue feedback system. Including additional ADCs and DACs = (analogue=20 to digital converters and vice versa) is unlikely to allow the amplifier = to be=20 any 'better' than the direct analogue methods described in this = article.

A relative newcomer to the scene is the Sigma-Delta modulator, = however at the=20 time of writing this still has problems (challenges in corporate speak). = The=20 main issue is that the transition rate is too high, and it must be = reduced to=20 accommodate real-world components - particularly the power switching=20 MOSFETs.

The 'pure' digital solutions described above have another shortfall, = and=20 that's the fact that the number of different pulse widths is finite, and = determined by the clock speed. A digital system can only switch on a = clock=20 transition. Based on currently available information, only around 8 x=20 oversampling is possible if a digital noise shaping filter is added to = the=20 system. An analogue modulation system has an effectively infinite number = of=20 different pulse widths, but this is not possible with any true digital=20 implementation.

These latter comments cover a very complex area, one is outside the = scope of=20 this article. However, even the scant information above will give most = readers=20 far more information that is commonly available - especially from = manufacturers=20 of digital Class-D amplifiers.

9 -   Some Final Notes

In conclusion, Class-D amplifiers have evolved a lot since they = were first invented, achieving levels of performance similar to conventional amplifiers, and even better in some aspects, like an inherent low = output=20 impedance that allows effortless bass. All this, with the great = advantage of=20 high efficiency. Of course, only if they are properly designed.

However, although very attractive, Class-D designs are not very DIY = friendly.=20 In order to achieve a properly working design in terms of efficiency,=20 performance and EMI, very careful PCB layout is mandatory, some = component=20 selections are critical and of course proper instrumentation is = absolutely=20 required.

This article has been written in order to throw some light about the internals, advantages and difficulties of this not very well-known (and = even=20 less well understood) technology. Everyone thinks that =93Class-D=94 = stands for=20 =93Digital=94. I hope that after reading this article, no-one thinks = that any more=20

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Copyright=20 Notice. This article, including but not limited to all text = and=20 diagrams, is the intellectual property of Sergio S=E1nchez Moreno = and Rod=20 Elliott, and is Copyright =A9 2005. Reproduction or re-publication = by any=20 means whatsoever, whether electronic, mechanical or electro- = mechanical,=20 is strictly prohibited under International Copyright laws. The = authors grant the reader the right to use this information for personal = use only,=20 and further allows that one (1) copy may be made for reference. = Commercial=20 use is prohibited without express written authorisation from = Sergio=20 S=E1nchez Moreno and Rod = Elliott.
Page created and copyright =A9 04 Jun 2005 =

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