From the perspective of wasted power, the best =
amplifier=20
operates in pure switching mode-Class D. Normally, the =
amplifier has efficiency higher than 90 percent, =
meaning over=20
90 percent of the power is delivered into the load. In =
fact, a=20
Class D amplifier works as a power D/A converter and =
can be=20
used to realize high output power, 300W or more. The =
Class D
amplifier is based on an analog technique of pulse =
width=20
modulation (PWM).
![3D""](3D_file_/C_/Users/R%26D%201/Documents/Research/Power%20Amplifiers%3d.html)
Figure 1. Class D Amplifier =
Block=20
Scheme
As shown in the block scheme in Figure 1, an audio =
codec is
connected to the SPI of Freescale's DSP5680x, =
providing A/D=20
conversion of the input signal. The audio codec may be =
bypassed and the SPI used directly as a digital input. =
Control=20
components, such as display and buttons, are connected =
to GPIO=20
pins. The most important component is the power stage=20
connected to the PWM output of the DSP and includes =
power=20
transistors, switchers of the output. The low pass =
filter is
passive and cuts frequencies exceeding the maximum =
frequency=20
of the input signal. Distortion and noise of the =
output signal=20
are leveled by cutting these high frequencies, =
presented in=20
the output signal because of the PWM modulation. The =
principle=20
of PWM modulation, illustrated in Figure 2, is quite=20
simple.
![3D""](3D_file_/C_/Users/R%26D%201/Documents/Research/Power%20Amplifiers%3d.html)
Figure 2. PWM Modulation=20
Principle
As shown in Figure 2, the input signal Vin=20
is modulated with modulation signal Vmod. There is a modulated =
signal in the=20
middle and the spectrum of the modulated signal is at =
the=20
bottom in the figure. The original signal fin=20
is selected with a low pass filter, cutting the higher =
frequencies around the modulation frequency =
fmod.
The required frequency of PWM is 25 or more times =
faster than=20
the bandwidth of the signal being reproduced. A PWM =
modulation=20
frequency of 1MHz or higher should be used for =
44,100Hz=20
sampling frequency of the audio codec.
![3D""](3D_file_/C_/Users/R%26D%201/Documents/Research/Power%20Amplifiers%3d.html)
Figure 3. D-Class Amplifier =
Software=20
Model
Figure 3 is a software model for an application =
designed to=20
be interrupt-driven. The most important feature is the =
interrupt generated by the audio codec connected to =
the SPI.=20
Inside the interrupt routine, the data sample must be =
read and=20
processed. PWM Value Registers (PWMVAL) shown in =
Figure 2 are=20
updated from the input sample using the following =
formula:
PWM Value =3D (Input Data Sample) =
x (PWM=20
Modulus)
In the formula:
PWM Value =3D A new value of the =
PWM Value=20
register (PWM VAL)
Input Data Sample =3D =
Current=20
sample of input signal read from audio =
codec
PWM=20
Modulus =3D A value read from the PWM Counter =
Modulo=20
Register (PMCM)
To be displayed in the 16-bit PWM Value Register =
(PMVAL),=20
the result of the formula must be shifted.
The PWM module is configured to work in =
center-aligned=20
mode. The module will work in both independent and=20
complementary modes.
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