No.
|
Mark
|
I/O
|
Function
|
1
|
BCLK
|
O
|
N.C.
|
2
|
LRCK
|
O
|
N.C.
|
3
|
SRDATA
|
O
|
N.C.
|
4
|
DVDD1
|
I
|
Power supply input (for digital circuit)
|
5
|
DVSS1
|
I
|
GND (for digital circuit)
|
6
|
TX
|
O
|
Digital audio interface signal output (Latches data at first transition)
|
7
|
MCLK
|
I
|
Microprocessor command clock signal input
|
8
|
MDATA
|
I
|
Microprocessor command data signal input
|
9
|
MLD
|
I
|
Microprocessor command load signal input
|
10
|
SENSE
|
O
|
Sense signal output (OFT, FESL,MAGEND,/NAJEND,POSAD,SFG) (Not used, open)
|
11
|
/FLOCK
|
O
|
Focus servo feeding signal output (L : Feed)
|
12
|
/TLOCK
|
O
|
Tracking servo feeding signal output (L : Feed)
|
13
|
BLKCK
|
O
|
Sub-code block clock signal output (BLKCKf = 75Hz during normal playback)
|
14
|
SQCK
|
I
|
External clock signal input for sub-code Q resistor
|
15
|
SUBQ
|
O
|
Sub-code Q code output
|
16
|
DMUTE
|
I
|
Muting input (H : mute)
|
17
|
STAT
|
O
|
Status signal output(CRC,CUE,CLVS,/TTSTVP,FCLV,SQCK)
|
18
|
/RST
|
I
|
Reset signal input
|
19
|
SMCK
|
O
|
1/2-diveded clock signal of crystal osscillating at MSEL = H (fSMCK = 8.4672 MHz) 1/4-divided clock signal of crystal oscillating at MSEL = L (fSMCK = 4.2336MHz)
|
20
|
CSEL
|
I
|
Frequency Selection Terminal H = 33.8688 MHz ; L = 16.9344 MHz
|
21
|
TRV
|
O
|
N.C
|
22
|
TVD
|
O
|
Traverse drive output
|
23
|
PC
|
O
|
Spindle motor ON output ("L" : ON)
|
24
|
ECM
|
O
|
Spindle motor drive signal output(forced mode output)
|
25
|
ECS
|
O
|
Spindle motor drive signal output(servo error signal output)
|
26
|
KICK
|
O
|
N.C.
|
27
|
TRD
|
O
|
Tracking drive output
|
28
|
FOD
|
O
|
Focus drive output
|
29
|
VREF
|
I
|
D/A (drive) output (TVD, ECS, TRD, FOD, FBAL, TBAL) Reference voltage input
|
30
|
FBAL
|
O
|
Focus balance adjustment output
|
31
|
TBAL
|
O
|
Tracking balance adjustment output
|
32
|
FE
|
I
|
Focus error signal input (analog input)
|
33
|
TE
|
I
|
Tracking error signal input (analog input)
|
34
|
RFENV
|
I
|
RF envelope signal input
|
35
|
VDET
|
I
|
Vibration detection signal input ("H" :detection)
|
36
|
OFT
|
I
|
Off-track signal input ("H" : off track)
|
37
|
TRCRS
|
I
|
Track cross signal input
|
38
|
/RFDET
|
I
|
RF detection signal input ("L" : detection)
|
39
|
BDO
|
I
|
Dropout signal input ("H" : Dropout)
|
40
|
LDON
|
O
|
Laser on signal output ("H" : ON)
|
41
|
PLLF2
|
I/O
|
N.C.
|
42
|
DSLF2
|
O
|
Tracking Offset alignment output/DSL Balance Output (DA Output)
|
43
|
WVEL
|
O
|
N.C.
|
44
|
ARF
|
I
|
RF signal input
|
45
|
IREF
|
I
|
Reference current input
|
46
|
DRF
|
I
|
DSL bias terminal (Not used, open)
|
47
|
DSLF
|
I/O
|
DSL loop filter terminal
|
48
|
PLLF
|
I/O
|
PLL loop filter terminal
|
49
|
VCOF
|
I/O
|
VCO loop filter terminal
|
50
|
AVDD2
|
I
|
Power supply input (for analog circuit)
|
51
|
AVSS2
|
I
|
GND (for analog circuit)
|
52
|
EFM
|
-
|
EFM signal output
|
53
|
PCK
|
-
|
PLL extraction clock output (fPCK = 4.321 MHz during normal playback)
|
54
|
VCOF2
|
I/O
|
VCO Loop filter for 33.8688 MHz conversation terminal for 16.9344 MHz crystal mode, must use other circuit
|
55
|
SUBC
|
O
|
Sub-code serial data output
|
56
|
SBCK
|
I
|
Clock input for sub-code serial data
|
57
|
VSS
|
I
|
GND
|
58
|
X1 IN
|
I
|
Crystal oscillating circuit input (f = 16.9344MHz)
|
59
|
X2 OUT
|
O
|
Crystal oscillating circuit input (f = 16.9344 MHz)
|
60
|
VDD
|
I
|
Power supply input (for oscillating circuit)
|
61
|
BYTCK
|
-
|
Byte clock output
|
62
|
/CLDCK
|
-
|
Sub-code frame clock signal output (fCLDCK = 7.35 kHz during normal playback)
|
63
|
FCLK
|
-
|
Crystal frame clock signal output (fCLK = 7.35 kHz, double = 14.7 kHz)
|
64
|
IPFLAG
|
-
|
Interpolation flag output (H : Interpolation)
|
65
|
FLAG
|
-
|
Flag output
|
66
|
CLVS
|
-
|
Spindle servo phase synchronizing signal output ("H" : CLV, "L" : rough servo)
|
67
|
CRC
|
-
|
Sub-code CRC checked output (H :OK, L :NG)
|
68
|
DEMPH
|
-
|
De-emphassis ON signal output (H :ON)
|
69
|
RESY
|
-
|
Frame re-synchronizing signal output
|
70
|
IOSEL
|
I
|
Mode Switching Terminal
|
71
|
/TEST
|
I
|
Test input
|
72
|
AVDD1
|
I
|
Power supply input (for analog circuit)
|
73
|
OUTL
|
O
|
Left channel audio signal output
|
74
|
AVSS1
|
I
|
GND
|
75
|
OUTR
|
O
|
Right channel audio signal output
|
76
|
RSEL
|
I
|
RF signal polarity assignment input (at "H" level, RSEL="H", at "L" level, RESL="L")
|
77
|
IOVOD
|
I
|
5V supply input
|
78
|
PSEL
|
I
|
Test terminal (connected to Gnd)
|
79
|
MSEL
|
I
|
SMCK oscillating frequency designation input (L:4.2336 MHz, H:8.4672 MHz)
|
80
|
SSEL
|
I
|
SUBQ output mode select (H:Q-code buffer mode)
|