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Magnus Eventide page=20
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Magnus Eventide Page
H949 User and Service Manual
Front sheets
I=20
Front cover
II=20
Warranty Page
III=20
Warranty Registration Form (now slightly out of date)=20
User Manual
1=20
Tables of Content, Introduction
2=20
Control Description, Power On/Off, Line In/Out
3=20
Input Level Control and Indicator Group, Repeat Control, Feedback =
Control=20
Group
4=20
Delay Only Output (MSEC) Switch Group, Pitch Control/Readout Group
5=20
Function Select Switch Group
6=20
Pitch Control Group
7=20
Delay/Random/Flange/Reverse Functions
8=20
Main Output (MSEC) Delay Set Switch Group, Algorithm Select 1/2
9=20
Remote Control, Voltage Control of Pitch Ratio
10=20
Resistive Control of Pitch Ratio, Frequency Control of Pitch Ratio
11=20
Rear Panel Connectors, Grounding
12=20
(cont)
13=20
(cont)
14=20
(cont)
15=20
HK940 - Keyboard fpr Eventide Harmonizer Model H910 and H949
16=20
(cont)
Technical Section
TS=20
D i Tables of Content, Introduction
TS=20
D ii (cont)
T1=20
Alignment Instructions
T2=20
(cont)
T3=20
Service Section, Introduction to Service Section
T4=20
(in=20
200 DPI) Power Supply
T5=20
HA931 basic layout
T6=20
Audio Processing, Input Processing, Output Processing, Pitch Change =
Timing and=20
Control Circuitry
T7=20
Read Fifo Clock Select, Voltage Controlled Oscillator (VCO)
T8=20
(cont)
T9=20
Single Side Band Generator - SSB
T10=20
Voltage Controlled Quadrature Oscillator
T11=20
Pseudo Random Noise Generator, Tape Capstan Drive, Audio Level =
Display
T12=20
HD921 basic layout
T13=20
Master Oscillator, Program Counter, Timing PROM, Central Processing Unit =
(CPU)
T14=20
Micro-Instruction (uINST) PROMs
T15=20
Conditional Micro-Instructions, Conditional CPU Register Addresses
T16=20
Status Flags, CPU Data Input, CPU Analog Output
T17=20
11x16k Dynamic RAM Array, Analog-To-Digital Converter (ADC), Delay Only=20
Output
T18=20
Fixed Delay Output, First-In First-Out (FIFO) Registers, Main Output =
DAC
T19=20
Main Output Reference Voltage
T20=20
HP941, Input Level, Feedback, Delay Set Switches, Function Select, =
Algorithm=20
Select
T21=20
Control Mode Select, Pitch Ratio Readout
S1=20
Master Block Diagram
S2=20
Input Audio Processing, Output Audio Processing
S3=20
Pitch Change Timing & Control, System Timing & Central =
Processing=20
Unit
S4=20
(in=20
200 DPI) HA931 1/6 - Input Audio Processing
S5=20
HA931 2/6 - Output Audio Processing
S6=20
HA931 3/6 - Voltage Controlled Oscillator and Read FIFO Clock =
Select
S7=20
HA931 4/6 - Single Side Band Generator
S8=20
HA931 5/6 - Function Select Logic, Audio Level Indicators, Pseudo Random =
Noise=20
Generator, Capstain Drive and Display Timing Circuitry
S9=20
HA931 6/6 - Power Supply
S10=20
HD921 1/7 - Master Oscillator, Program Counters and Analog-To-Digital=20
Converter
S11=20
(in=20
200 DPI) HD921 2/7 - Timing and Micro-Instruction Programmable=20
Read-Only-Memories (PROMs)
S12=20
HD921 3/7 - CPU Status Flags and Conditional uINSTR Logic
S13=20
HD921 4/7 - 16-bit Central Processing Unit (CPU) and 11x16k Dynamic =
Random=20
Access Memory Array (RAM)
S14=20
HD921 5/7 - Data PROM, CPU Analog Out and RAM Address and Timing
S15=20
HD921 6/7 - FIFO Array and Timing, Main Output DAC
S16=20
HD921 7/7 - Main Output Reference Voltage and Delay Only DAC
S17=20
HP941 1/2 - Audio Control and Delay Set
S18=20
HP941 2/2 - Function Select, Control and Display
S19=20
(in=20
200 DPI) dbx Model 303C Type II schematic
S20=20
Inter-Board Connectors
S21=20
Ribbon Cable Harnesses
S22=20
Integrated circuits used in H949 Harmonizer
S23=20
(cont)
S24=20
(cont)
S25=20
(cont)
S26=20
Last Page - The End
Magnus =
Danielson <cfmd at bredband dot=20
net>