|
|
User's Manual forANC-3089Ethernet Interface Adapter=The photo above is linked =
to the
specific datasheet for
|
|
SIP Pin #<= /span> |
Function |
Comment |
Data Direc= tion |
|
1 |
Primary +power |
+5 V DC |
input to adapter= |
|
2 |
Primary ground |
Ground |
input to adapter= |
|
3 |
Secondary ground= |
Ground |
input to adapter= |
|
4 |
Secondary +power= |
+5 V DC |
input to adapter= |
Connect the +5v DC power to pin 1 and the mating power supply ground to pin 2 of = J1. Only 2 pins are needed to power the adapter, the other 2 secondary pins a= re not needed on the current PCB design.
E=
thernet
Connection
The RJ-45 connector, J2, provides the a=
ctual
connection to the ethernet. The pinouts from the connector are standard a=
nd
should interface with CAT-5 cable mated with 8-pin RJ-45 male connectors
wired for ethernet use. Note pin 6 is RC-, not pin 4 and that pin 4 is
shorted to pin 5 and pin 7 is shorted to pin 8.
|
RJ-45 pin = # |
Function |
Comment |
Data Direc= tion |
|
1 |
TX+ |
Transmit plus |
Output from adap= ter |
|
2 |
TX- |
Transmit minus |
Output from adap= ter |
|
3 |
RC+ |
Receive plus |
Input to adapter= |
|
4 |
|
Shorted to pin 5= |
See schematic |
|
5 |
|
Shorted to pin 4= |
|
|
6 |
RC- |
Receive minus |
Input to adapter= |
|
7 |
|
Shorted to pin 8= |
See schematic |
|
8 |
|
Shorted to pin 7= |
|
Hardware Wiring
The 40-pin connector J3 is the interface
between the ANC-3089 ethernet card and the designer’s microprocesso=
r,
microcontroller or DSP chip. To ease this process, and offer a universal =
way
to connect to the card, there are 3 ways the adapter may be interfaced. By
using a standard 40-pin IDC ribbon cable, the user can connect to the car=
d in
applications where the ANC-3089 is mounted separate from the target proce=
ssor
controlling it. An example would be where the adapter is mounted within a
piece of equipment with the RJ-45 connector sticking out of the back to
access the ethernet. For prototyping, J3 can also be accessed on the oppo=
site
side of the PCB for applications where a daughter board arrangement is
preferred. The bottom side 0.018" diameter machine pins plug into
standard 0.1" center-to-center component sockets or mating machine p=
in
sockets. Lastly, we have included wire wrap posts for both J1 and J3 to u=
se
in wire wrapping prototypes of initial designs.
Data and Control
The ANC-3089 adapter can be viewed as a
40-pin peripheral chip. The Cirrus CS8900A ethernet chip is addressed as
eight 16-bit memory mapped registers. The designer needs to generate a
negative-true chip select to pin 17 (AEN) and suitable negative-true
read/write memory signals. The table below shows the pinouts of the 40-pin
connector and figure 3 below is a physical map of the pin connections. Be
aware of the timing for the data, address and read/write signal to insure=
the
processor you are using generates signals conforming with the minimums and
maximums needed by the CS8900A for reliable operation.
8-Bit Mode
For minimum interfacing with an 8-bit
processor, 16 signal lines for data and control are required. The 8 data
lines (D0-D7), 4 address lines (A0-A3), plus the reset, chip select (AEN),
write data (WR*) and read data (RD*) control the adapter operation. Readi=
ng
or writing to the 16-bit registers is performed 8-bits at a time loading =
an
upper and lower byte to form the 16-bits used internally by the CS8900A. =
Note
that the byte order that data is written or read to/from the CS8900A is
important and depends upon if data or control information is being proces=
sed.
Check with the appropriate application note from Cirrus detailing 8-bit
operation (AN181) for how this is done. Interrupts are not usable in
8-bit mode so the designer should poll the CS8900A for complete frames. T=
here
is 2K worth of input buffer space, so while a frame is being processed,
additional frames can be input without interruption. If every pack=
et
was input on a network with heavy traffic, the processor would probably n=
ot
be able to keep up - with or without an interrupt signaling that a new fr=
ame
had arrived. Filtering and disabling the ‘promiscousA’ bit of
Receive Control Register (104H) will limit the number of frames stored to=
the
on board RAM buffer to those frames being directed to the individual MAC
address of the adapter. The Receiver Event Register (4H) has a
’IndividualAdr’ bit which can be tested to identify frames se=
nt
to the adapter’s MAC also. See Appendix B which shows a typical 8-b=
it
interface for the 8051 family of processors.
16-Bit Mode
For 16-bit applications, connect SBH=
E*
(pin 23) to AEN (pin 17). The toggling of the SBHE* line is what sign=
als
the CS8900A chip to use the upper 8-bits in addition to the lower 8-bits =
for
data and control operation. In addition to the address and control lines
detailed above all of the 16 data lines (D0-D15) are connected to the
processor. In 16-bit operation, an interrupt can be set up to signal frame
activity on pin-26 (INTR).
|
pin # (J2) |
FUNCTION |
Comment |
pin # (J2) |
FUNCTION |
Comment |
|
1 |
D7 |
MSB of 8-bit dat= a bus |
2 |
Reset |
Reset pulse neg/= pos |
|
3 |
D6 |
|
4 |
Ground |
Digital ground |
|
5 |
D5 |
|
6 |
Ground |
|
|
7 |
D4 |
|
8 |
Ground |
|
|
9 |
D3 |
|
10 |
Ground |
|
|
11 |
D2 |
|
12 |
Ground |
|
|
13 |
D1 |
|
14 |
Ground |
|
|
15 |
D0 |
LSB of 8-bit dat= a bus |
16 |
Ground |
|
|
17 |
AEN |
Chip select - ne= g |
18 |
A3 |
MSB Address line= |
|
19 |
WR* |
Write data pulse= - neg |
20 |
A2 |
|
|
21 |
RD* |
Read data pulse = - neg |
22 |
A1 |
|
|
23 |
SBHE* |
8 or 16-bit oper= ation |
24 |
A0 |
LSB Address line= |
|
25 |
D8 |
LSB of upper byt= e |
26 |
Interrupt= |
Interrupt (16-bi= t use) |
|
27 |
D9 |
|
28 |
Ground |
|
|
29 |
D10 |
|
30 |
Ground |
|
|
31 |
D11 |
|
32 |
Ground |
|
|
33 |
D12 |
|
34 |
Ground |
|
|
35 |
D13 |
|
36 |
Ground |
|
|
37 |
D14 |
|
38 |
Ground |
|
|
39 |
D15 |
MSB of 16-bit bu= s |
40 |
Ground |
|
neg =3D negative tr= ue logic (logic low to enable function)
figure
3 - J3, Data and Control Signal Map
The connector map above is useful in quickly identifying the pinouts on the 40-pin processor interface. Only 1= 6 pins are needed to interface an 8-bit processor to the ethernet. When a 40-pin ribbon cable is used, there is a ground pin placed between most of the da= ta lines to provide faraday shielding.
Addressing
The logical card address detailed in the
CS8900A documentation refers to the default address range of 300H to 30FH=
to
control the operation of the chip. The adapter is hard wired to the base
address 300H to match the power up default of the CS8900A chip. The physi=
cal
address of the ANC-3089 adapter is controlled by the user to be decoded by
using the AEN as a low logic chip select and the A0 to A3 lines to form t=
he
lower 4-bits of the address. The adapter can be driven as an I/O or memory
mapped peripheral. Referring to Appendix B, the schematic shows the adapt=
er
being decoded by inverting the A15 line as a chip select, and using the A=
8 to
A11 lines from the 8052 processor to drive the A0 to A3 adapter lines. Th=
is
example provides a simple interface requiring a minimum of external circu=
itry
to map the logical 300H-30FH range to the physical 8000H-8F00H in the
8052’s memory space.
Software
The adapter is a special purpose embedd=
ed
processor that is equipped with the analog and digital circuitry needed to
physically connect with the ethernet, an IEEE-802.3 MAC engine and extern=
al
processor interface. The ethernet packets processed by the CS8900A are
formatted frames written and read from the processor interface. The ether=
net
adapter does not know the information content of the frames, only that th=
ey
have been input through the ethernet interface, or transferred from the
processor connected to the 40-pin connector for transmission. It is up=
to
the processor running the ANC-3089 to input, check and decode the incoming
frames and generate the proper ethernet frame output messages (called
datagrams in ethernet-speak). Like most other microprocessor or
microcontroller peripheral chips, the ANC-3089 needs to be initialized af=
ter
power up for the desired mode of operation and then, as appropriate, act =
on
or control the end application. For more detailed software operation, ref=
er
to the documents listed under the Overview section on page 3.
The ethernet software required is a function of the user end application. An example would be to use the card= in a system that monitors some analog condition (like temperature), and then send an email to a preset email address when a upper or lower limit is exceeded. In such an application SMTP, a common email protocol, would be coded by the programmer to generate and send out mail datagrams over the ethernet interface to a locally connected IP address, or a gateway to the internet to be transmitted anywhere in the world. Another example is using the adapter to interface to a computer driven telescope. Here the designer would probably use User Defined Protocol (UDP) to send commands to the telescope for object selection and receive JPEG images back from the telescope’s eyepiece mounted CCD camera.
Appendix A - Troubleshooting Guide
Here are some common sources of
problems and tests you can make to diagnose your ethernet interface.
Application Note - AP205 from Cirrus (cirrus.com) should also be download=
ed
and looked over.
Powering
Be sure that the +5v DC power is being
applied to the card. The right-hand side green ‘LINK’ LED sho=
uld
be on even if there is no ethernet data or software running on the adapter
card if either a loopback or ethernet cable is connected to the on board
RJ-45 connector.
Interface Wiring
Check that all of the processor to adap=
ter
signal wires are connected correctly. A missing connection and/or a miswi=
red
connection is a common mistake. If is somewhat harder to do, but connecti=
ons
can be shorted also. Any of the above will cause the adapter to appear no=
t to
work at all.
Loopback Test
Without having an external network runn=
ing,
the designer can use a loopback test using a short RJ-45 cable with the T=
X+
connected to the RC+ and the TX- to the RC-. Initialize the CS8900A chip =
for
‘‘promiscousA’ mode and "full duplex" operati=
on
so that any frame transmitted will be received and read in. Then generate=
a
transmission and check the received message. Using an in-circuit emulator=
to
replace the processor being interfaced with the adapter will speed up the
process. If you are able to read a loopback transmission, the adapter is
working.
CABLING
On the RJ-45 connector the right-hand s=
ide
green ‘link’ LED should be on if the cable going from the RJ-=
45
is connected to an ethernet signal source, like a hub. The other green
‘frame activity’ LED on the left-hand side of the RJ-45 will =
wink
on for 6ms when a frame is received or transmitted. Even if the CS8900A c=
hip
is not initialized and just powered up, those 2 LEDs should function as
described.
If one of the interface wires used i= s not connected (open) or shorted to another wire, the whole interface will app= ear not to be working. Try using another cable or the loopback test described above through the cable to verify operation. If you can not get the loopb= ack test to work through the cable, it will not work in your application. Even cables purchased with molded ends can be damaged or, as described in the = next sentence, not wired right.
The cable wiring should use twisted = pairs of wires for transmit on pins 1 and 2 while the receive pair is pin 3 and= 6 (not pin 4). Be sure to verify that any purchased cables follow that wiri= ng, many do not.
Jumpers - RESET and LED Enable
Make sure that jumper 2 is set so that =
the
signal being applied to the ethernet chip ‘RESET’ is normally
low. If it is being held high, the ethernet chip will not operate.=
If none of the LEDs work, check that= JP1 has a shunt across the two pins enabling power to the LEDs.
Program Operation
The ethernet adapter handles the transm=
itted
and received frames, but the processor must interpret and generate the da=
ta
as the ethernet chip has no idea of the actual frame content or meaning. =
Make
sure the CS8900A is being initialized properly for the mode of operation =
you
intended and that data being sent and received is properly formatted for =
the
protocol you are working with. If the program is not setup right, the
adapter will appear not to be working at all.
Chip Timing
Be aware of the timing for the data, ad=
dress
and read/write signal to insure the processor you are using generates sig=
nals
conforming with the minimums and maximums needed by the CS8900A for relia=
ble
operation. A fast 8051 processor may be generating a RD* or WR* signal th=
at
is too short for the CS8900A to act on. Such timing problems can be solve=
d by
generating the control signals in software rather than using the hardware
signals of the processor.
Now What?
If none of the above seems to fix the
problem, but both green LEDs are working as described above in the
"CABLING" heading, the adapter is probably working and you may =
now
need to examine and monitor the signals with an oscilloscope and use an
ethernet frame analysis software tool to examine the transmitted and rece=
ived
ethernet data packets. Each adapter is tested before shipping on a PC wit=
h an
ethernet interface card running through a hub connected to a 40’ CA=
T-5
cable. Like everything, occasionally an adapter can go bad because they a=
re
damaged in shipping or infant component burnout. We do warranty our adapt=
ers,
so if it still does not work, call Antona and we will work out an adapter
exchange.
Appendix B - 8052 Interface Example
Here is an example showing how to inter=
face
an 8052 microcontroller with the ANC-3089 ethernet adapter.
figure
4 - 8052 interface example
The adapter is addressed as ex= ternal memory beginning at location 8000H and uses the 8052’s A8-A11 addre= ss lines to control the adapter’s A0-A3 address lines for directing control and data to the CS8900A registers. This uses a single section of a 74LS04 to invert the A15 line from P2.7 of the 8052 pictured above. The designer could use P1.6 as a chip select clearing then setting the bit wh= en I/O is being performed to the adapter and do away with the added inverter. This simple minded interface allows 3 more memory mapped peripherals to be added (useful for making the system actually do something) by using the A12, A13 and A14 (P2.4, P2.5, P2.6) address lines on the 8052 as additional chip selects. P1.7 is used as a software controlled reset line= to the CS8900A and P3.6 / P3.7 furnish the respective write and read signals= If higher speed processors are being used, it may be necessary to drive the write and read signals with software generated pulses because the CS8900A requires a minimum pulse width of 135ns.
Appendix C -Circuit Board Schematic
The following page contains the sche=
matic
for the 3089 adapter. The schematic and card artwork are copyright protec=
ted
by Antona Corporation and are included only to aid the end user to config=
ure
the adapter or for competent technical service personnel to use in
maintenance or repair.
Note: The schematic is included with the purchase of the product=
.
Related Links
Updated 04/10/03 23:00 =
Copyright © 2003 Antona Corporation, L.A., CA., U. S. A.