Welcome back to Timing is Everything! Last time we covered Understanding PLL loop filter response. Today, I =
will be=20
helping you learn how to better understand the variety of jitter=20
specifications.
As timing requirements in high-speed =
applications become=20
tighter and more stringent, a more developed understanding of the =
various jitter=20
specifications is highly essential; from 10 Gbit Ethernet networks to =
high-speed=20
interconnects such as PCIe, robustness implied in the links is closely =
tied to=20
reducing timing margins.
In short, jitter is the deviation of signal edges from an =
=E2=80=9Cideal=E2=80=9D value or=20
interval. Using a periodic signal as our ideal reference, a =
=E2=80=9Creal=E2=80=9D signal=20
in a system with noise contributions from sources such as power =
supplies,=20
thermal noise, and cross coupling interferences is more accurately =
described in=20
the images below. Figure 1 is the =E2=80=9Cideal=E2=80=9D signal, with =
the frequency domain=20
representation of the signal also shown.
Figure 1: The =E2=80=9Cideal=E2=80=9D =
signal
As noise and perturbations affect the signal, the resultant waveform=20
undergoes the effect of jitter, as shown in Figure 2. The spreading of =
the=20
signal's energy across the frequency spectrum is known as phase =
noise.
Figure 2: Effects of jitter
Jitter can be further broken down into several subclasses and =
specifications,=20
each with its own properties and measurement techniques. The major =
measurement=20
techniques are as follows: period jitter, cycle-to-cycle period jitter =
and phase=20
jitter. While these are not all of the forms of measurement, we will =
focus on=20
only these in this short dissection.
Period Jitter
Period jitter is the deviation of cycle duration with respect to the=20
aforementioned ideal signal's period. By randomly selecting a number of =
cycles,=20
we can then calculate the average clock period (which should approach =
the ideal=20
period=E2=80=99s duration) as well as the standard deviation and =
peak-to-peak values.=20
The standard deviation is referred to as the =E2=80=9CRMS =
jitter=E2=80=9D and the peak-to-peak=20
value is referred to as the =E2=80=9CPk-Pk period jitter.=E2=80=9D
Because of period jitter=E2=80=99s random Gaussian distribution, its =
energy contents=20
are fully described by the mean and standard deviation; however, a more =
useful=20
measurement is derived from the Pk-Pk period jitter. Knowing the Pk-Pk =
period=20
jitter is useful when appropriately configuring system setup and hold =
times. The=20
following equation approximates this worst case scenario:
Pk-Pk period jitter =3D 2=CF=83 x (RMS period =
jitter)
The appropriate value of =CF=83 is derived from the Gaussian =
distribution=20
probability density function, shown in Table 1. The table reads as =
follows: for=20
a given sample size N cycles, N-1 of those samples cycles =
will be=20
have a period within =CF=83N of the mean value of the =
distribution.=20
Only then will one cycle of N cycles fall outside of that range. =
Bit=20
Error Rate is used directly where BER =3D =
1/N.
Table 1: Gaussian distribution =
probability
Cycle-to-Cycle Jitter
Cycle-to-cycle jitter is the variation of the cycle time of two =
adjacent=20
cycles in a periodic signal. The adjacent cycles are randomly chosen =
throughout=20
the signal stream until enough samples have been collected =E2=80=93 =
typically 1,000+=20
samples. The peak deviation in the adjacent cycle sets is reported as=20
cycle-to-cycle jitter and is especially useful in spread spectrum =
clocking where=20
period jitter is highly susceptible to intentional frequency =
spreading.
Phase Jitter and Phase Noise
When looking at the frequency domain representation of the signal of=20
interest, noise values at specific offset frequencies (with respect to =
the=20
carrier) are known as the phase noise. An example of this -110 dBc/Hz at =
12 MHz=20
offset or -70 dBc/Hz at 50 kHz offset.
Taking the discrete phase noise points over a band of interest and=20
integrating results in the phase jitter of a signal is described in the =
equation=20
below. Here, f0 is the carrier and =
f1=20
and f2 are the limits of the integration bandwidth =
on only=20
one side of the carrier (it is assumed the signal is symmetric).
The importance of this measurement is similar to that of periodic =
jitter,=20
only here the distribution of periods is generated by their respective=20
frequencies (hence the wider spread of energy in both Figures 1 and 2). =
With=20
respect to the communications systems as well as ADCs and DACs, both =
receiver=20
and transmitter in conjunction create a band-pass-filter for through =
which=20
acceptable noise figure of merit can be created.
Time Interval Error (TIE)
Time Interval Error refers to the time deviation of the measured =
signal with=20
respect to an =E2=80=9Cideal=E2=80=9D signal. Figure 3 shows how TIE is =
measured. Here, the=20
=E2=80=9Cideal=E2=80=9D signal period is typically generated by the =
measurement device from the=20
average period of the signal of interest. TIE is calculated as =
follows:
TIE =
measurements are=20
useful in applications in which the reference clock is recovered from a =
data=20
stream using a CDR (Clock/Data Recovery) circuit. Large TIE values are =
good=20
indicators that the recovered clock PLL is unable to keep up with change =
in the=20
signal data rate.
Figure 3: Time Interval Error=20
measurement
Thanks=20
for joining me on Timing is Everything! I hope you now have a better=20
understanding of jitter specifications. Please leave any questions or =
comments=20
about material covered in this post below, or head to the Clock and Timing Forum=20
in TI=E2=80=99s E2E=E2=84=A2 Community to get your specific application =
need or question=20
addressed!
Additional=20
resources: