When designing a high-performance data acquisition system, a diligent =
engineer carefully selects a precision analog-to-digital converter (ADC) and =
the=20
additional components needed for the analog front-end conditioning =
circuit.=20
After spending weeks designing, performing simulations and =
optimizing the=20
schematic, the designer quickly puts board layout together to meet a =
tight=20
deadline. A week later, the first prototype board is tested. To =
his or her=20
surprise, the circuit does not perform as expected.
Has this ever happened to you?
Optimal PCB layout is essential to obtain the expected performance of =
your=20
ADC. When designing circuits with mixed-signal devices, you should =
always start=20
with a good grounding scheme and partition the design into analog, =
digital and=20
power sections using optimal component placement and signal routing. =
The reference path is the most critical in ADC layout, because all=20
conversions are a function of the reference voltage. With a traditional=20
successive approximation register (SAR) ADC architecture, the reference =
path is=20
also the most sensitive, as the reference pin presents a dynamic load to =
the=20
reference source.
Since the reference voltage is sampled several times during each =
conversion,=20
high-current transients are present in this terminal where the =
ADC=E2=80=99s internal=20
capacitor array is switched and charged as the bit decisions are made. =
The=20
reference voltage must remain stable and settled to the required N-Bit=20
resolution during each conversion clock cycle, or linearity errors and =
missing=20
code errors may occur.
Figure 1 shows the current transients during the conversion phase on =
the=20
reference terminal for a classic 12-bit SAR ADC.
Figure 1. Current Transients on the =
Reference Pin of=20
a 12-Bit SAR ADC
Because of these dynamic currents, the reference pin requires good =
decoupling=20
using a high-quality bypass capacitor (CREF). The bypass =
capacitor is=20
used as a charge storage reservoir that can provide instantaneous charge =
during=20
these high-frequency transient currents. You should place the reference =
bypass=20
capacitor as close as possible to the reference pin and connect them =
using=20
short, low-inductance connections.
Figure 2 shows a board layout example for the ADS7851, a 14-bit, dual ADC with two independent =
internal=20
voltage references.
Figure 2. =
Layout example=20
for a Dual ADC with Two Independent Internal References
In this four-layer PCB board example, the designer used a solid =
ground plane=20
right underneath the device and partitioned the board into analog and =
digital=20
sections keeping the sensitive inputs and reference signals away from =
noise=20
sources. He bypassed the REFOUT-A and REFOUT-B reference outputs with =
10-=CE=BCF,=20
X7R-grade, 0805-size ceramic capacitors (CREF-x) for optimal=20
performance and connected them to the device using small 0.1-=E2=84=A6 =
series resistors=20
to keep the overall impedance low and constant at high =
frequencies. He=20
also used wide traces to reduce inductance.
I highly recommend placing CREF in the same layer as the =
ADC. You=20
should also avoid placing vias between the reference pins and the bypass =
capacitors. Each reference ground pin of the ADS7851 has an independent via connection to GND, =
and each=20
bypass capacitor has its own low inductance connection to the ground =
path.
If you=E2=80=99re using an ADC that requires an external reference =
source, you should=20
minimize the inductance in the reference signal path =E2=80=93 starting =
from the=20
reference buffer output to the bypass capacitor to the ADC=E2=80=99s =
reference input.=20
Figure 3 shows a layout example for the ADS8881, an 18-bit, SAR ADC using an external =
reference and=20
buffer. The designer kept the inductance between the reference =
capacitor=20
and the REF pin less than 2 nH by placing the capacitor within =
0.1-inches from=20
the pin and connecting it with wide 20 mil traces and multiple 15-mil =
grounding=20
vias. I recommend a single, 10-uF, X7R-grade, 0805-size ceramic =
capacitor with=20
at least a 10-V rating.
The trace length from the reference buffer circuit to the REF pin was =
kept as=20
short as possible to ensure fast settling response.
Proper decoupling of the REF pin is critical to achieve optimum =
performance.=20
In addition, keeping low inductance connections in the reference path =
allows the=20
reference driving circuit to remain stable and settled during the =
conversion=20
phase, getting you one step closer to obtaining your desired =
results.
Figure 3. Layout example for =
an ADC with=20
an External Reference and Buffer
For a deeper look into this topic, check out the Layout Guidelines =
provided=20
in the ADS8881 and ADS7851 datasheets.