From: "Saved by Internet Explorer 11" Subject: PCB Stack-Up - Part 2 Date: Thu, 2 Jul 2015 15:06:07 -0700 MIME-Version: 1.0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Location: http://www.hottconsultants.com/techtips/pcb-stack-up-2.html X-MimeOLE: Produced By Microsoft MimeOLE V6.1.7601.17609 =20 =20 =20 = PCB Stack-Up=20 - Part 2 =20

Henry Ott=20 Consultants

Electromagnetic Compatibility Consulting = and=20 Training

PCB Stack-Up

Part 2. Four-Layer = Boards

The most=20 common four-layer board configuration is shown in Fig. 1 (power and = ground=20 planes may be reversed). It consists of four uniformly spaced layers = with=20 internal power and ground planes. The two external trace layers usually = have=20 orthogonal trace routing directions.=20

           &nbs= p;    _____________ Sig.
            &= nbsp;   _____________ = Ground           &= nbsp;           &n= bsp;=20 Figure 1
            &= nbsp;   _____________ Power
            &= nbsp;   _____________ Sig.

Although this configuration is significantly better than a two-layer = board,=20 it has a few, less that ideal characteristics. With respect to the = list of=20 objectives in Part 1, this stack-up only satisfies objective (1). = If the=20 layers are equally spaced, there is a large separation between the = signal layer=20 and the current return plane. There is also a large separation = between the=20 power and ground planes. With a four-layer board we cannot correct = both of=20 these deficiencies at the same time; therefore, we must decide which is = most=20 important to us. As mentioned previously, with normal PCB = construction=20 techniques there is not sufficient inter-plane capacitance between the = adjacent=20 power and ground planes to provide adequate decoupling. The = decoupling,=20 therefore, will have to be taken care of by other means and we should = opt for=20 tight coupling between the signal and the current return plane. = The=20 advantages of tight coupling between the signal (trace) layers and the = current=20 return planes will more than outweigh the disadvantage caused by the = slight loss=20 in interplane capacitance.

Therefore, the simplest way to improve the EMC performance of a = four-layer board is to space the signal layers as close to the planes as = possible (<0.010"), and use a large core (>0.040") between the = power and=20 ground planes as shown in Fig. 2. This has three advantages and = few=20 disadvantages. The signal loop areas are smaller and therefore = produce=20 less differential mode radiation. For the case of 0.005" spacing = (trace=20 layer to plane layer), this can amount to 10 dB or more reduction = in the=20 trace loop radiation compared a stack-up with equally spaced = layers. =20 Secondly, the tight coupling between the signal trace and the ground = plane=20 reduces the plane impedance (inductance) hence reducing the common-mode=20 radiation from the cables connected to the board. Thirdly, the = close trace=20 to plane coupling will decrease the crosstalk between traces. For = a fixed=20 trace to trace spacing the crosstalk is proportional to the square of = the trace=20 height. This is one of the simplest, least costly, and most = overlooked=20 method of reducing radiation on a four-layer PCB. With this = configuration=20 we have satisfied both objectives (1) and (2).

&nbs= p; _____________ Sig.
&= nbsp; _____________ Ground

           &nbs= p;            = ;            =             &= nbsp;           &n= bsp;           &nb= sp;     Figure 2
            &= nbsp;   _____________ Power
            &= nbsp;   _____________ Sig.

What other possibilities are there for a four-layer board = stack-up? Well, we could become a little non-conventional and reverse the = signal=20 layers and the plane layers in Fig. 2, producing the stack-up shown in = Fig 3a.=20

&nbs= p; _____________ Ground.
&= nbsp; _____________ Sig.

           &nbs= p;            = ;            =             &= nbsp;           &n= bsp;           &nb= sp;       Figure 3a
            &= nbsp;   _____________ Sig.
            &= nbsp;   _____________ Power

The major advantage of this stack-up is that the planes on the outer = layers=20 provide shielding to the signal traces on the inner layers. The=20 disadvantages are that the ground plane may be cut-up considerably with=20 component mounting pads on a high density PCB. This can be = alleviated somewhat, by reversing the planes and placing the power plane on the = component side, and the ground plane on the other side of the board. = Secondly, some=20 people don't like to have an exposed power plane and thirdly, the buried = signal=20 layers make board rework difficult if not impossible. This = stack-up=20 satisfies objectives (1), (2), and partially satisfies objective (4). =

Two of these three problems can be alleviated with the stack-up shown = in Fig.=20 3b, where the two outer planes are ground planes and power is routed as = a trace=20 on the signal planes. The power should be routed as a grid, using = wide=20 traces, on the signal layers. Two added advantages of this = configuration=20 are that; (1) the two ground planes produce a much lower ground = impedance and=20 hence less common-mode cable radiation, and (2) the two ground planes = can be=20 stitched together around the periphery of the board to enclose all the = signal=20 traces in a faraday cage. From an EMC point of view this = configuration, if=20 properly done, is the best stack-up possible with a four-layer = PCB. Now we=20 have satisfied objectives, (1), (2), (4), and (5) while using only a = four-layer=20 board.

&nbs= p; _____________ Ground.
&= nbsp; _____________ Sig./Pwr.

           &nbs= p;            = ;            =             &= nbsp;           &n= bsp;           &nb= sp;      Figure 3b
            &= nbsp;   _____________ Sig./Pwr.
            &= nbsp;   _____________ Ground

A fourth possibility, not commonly used, but one that can be made to = perform=20 very well, is shown in Fig. 4. This is similar to Fig 2, but = with=20 the power plane replaced with a ground plane, and power routed as a = trace on the=20 signal layers.

&nbs= p; _____________ Sig./Pwr.
&= nbsp; _____________ Ground

           &nbs= p;            = ;            =             &= nbsp;           &n= bsp;           &nb= sp;       Figure 4
            &= nbsp;   _____________ Ground
            &= nbsp;   _____________ Sig./Pwr.

This stack-up overcomes the rework problem mentioned before, and = still provides for the low ground impedance as a result of two ground = planes. The planes however do not provide any shielding. This = configuration satisfies objectives (1), (2), and (5) but not objectives (3) or (4). =

So, as you can see there are more options available, than you might = have=20 originally thought, for four layer board stack-up. It is possible = to=20 satisfy four of our five objectives with a four layer PCB. The configurations of Figures 2, 3b, and 4 all can be made to perform well = from an=20 EMC point of view.

=A9 2000 Henry W. = Ott &nbs= p; = ; = Henry Ott Consultants, 48 Baker Road Livingston, = NJ 07039 (973) 992-1793

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Henry Ott Consultants

48 Baker Road Livingston, NJ 07039

Phone: 973-992-1793, FAX: = 973-533-1442

August=20 5, 2002