Tips for PCB Via Design
Basic theory
Vias are often part of the signal routing. They =
are=20
vertical connections between layers to simplify trace routing =
around other=20
components or when there is a high density of interconnections to =
be made=20
(i.e. BGA,=C2=B5BGA). As PCB trace, the PCB vias also have =
an associated=20
parasitic capacitance, inductance and impedance. These parasitic values =
can=20
be calculated as follow:
Capacitance: =
C=3D1.41=C3=97=CE=B5=C3=97T=C3=97D1/(D2=E2=80=90D1)=20
=20
[1] &=
nbsp; &n=
bsp; &nb=
sp;
Inductance:=20
L=3D5.08h=C3=97 [ln(4H/D1)+1] =
=20
[2]
where =CE=B5 is the =
relative=20
dielectric constant of PCB,
D1 is the =
diameter=20
of the via,
D2 is =
the diameter of=20
the anti=E2=80=90pad,
T is the thickness of the =
PCB, and=20
H is the length of the via.
Take a 1.6mm FR4 PCB (=CE=B5=3D4.4 below 500Mhz) as a example, =
one 0.254mm /=20
0.508mm via will=20
add
C=3D1.41=C3=974.4=C3=970.067=C3=970.02/(0.04=E2=80=900.02)=3D0.42p=
f capacitance and=20
L=3D5.08=C3=970.067=C3=97 [ln(4=C3=970.067/0.01)+1]=3D1.46nH =
inductance to the=20
trace.
These added capacitance and inductance will have the effect of =
more=20
time delay, longer rise and fall times of the signal, =
degrading=20
signal integrity. This maybe not a problem at lower frequencies =
designs.=20
However, it could become a critical issue in high speed printed=20
circuit board design.
Vias can also cause =
a=20
step=E2=80=90function change in trace impedance. A typical value of =
the impedance=20
drop on the via is about 10% (this could be variable depends on the =
via=E2=80=99s size,=20
pcb thickness, etc.,).
Take a 50ohm trace as =
example, the=20
reflection coefficient is (50=E2=80=9045)/(50+45)=3D5%.
As most high =
speed designs do=20
not carry more than several mA, the impact of via impedance is not =
vital as=20
the capacitance and inductance does.
Test and simulations done at www.quick-tech.co.uk = shows:
1.Less number of the vias on the trace results in shorter delay and =
quicker=20
rise time.
2. Smaller vias can get less delay, but =
not=20
significantly decreasing on the rise=20
time.
3. keeping the length of via shorter =
can get=20
less delay and quicker rise time.
Be noted the above summary is =
not=20
always right as the trace/via geometry maybe widely varied in the =
real=20
circuits. However most complicated topologies can be =
decomposed as=20
the combination of many trace + via + stub elements. =
Pre=E2=80=90layout=20
simulation with EDA tools is always a helpful way to analysis the =
critical=20
signals before PCB routing.
Practical guidelines:
The following via design guidelines using in PCB design process =
are=20
recommended to enhance the engineering performance, saving cost, =
increasing=20
the stability of the products.
Vias in high speed circuit =
design
1. Avoid using vias and layer changes if possible to avoid signal =
distortion.
2. Do not use via in high frequency clock =
transmission=20
line.
3. When possible, remove any unnecessary pads on vias =
because these=20
pads create parallel plate capacitance.
4. Smaller vias have =
lower=20
capacitance. Short length, larger diameter vias have =
lower inductance. Both=20
parasitic
elements can have detrimental affects, but =
it is=20
often the parasitic inductance element that provides an
=
=20
unexpected series impedance that creates signal transmission=20
problems.
5. Keep the number of vias of the two differential =
traces the=20
same to minimize the skew and phase difference.
Power/ground vias
For signal net, the bottleneck for the current carrying capacity =
is not=20
on the via. Check the capacity on the trace (line) to get the =
maximum=20
carrying capacity for the entire net.
For power net, the =
bottleneck is on=20
the via, the following are some thumb of rules:
0.25mm / =
0.50mm=20
Vias with 17um / 0.5oz copper weight, the maximum =
safety=20
current is 0.50A.
0.25mm / 0.50mm =
=20
Vias with 35um / 1.0oz copper weight, the maximum safety current =
is=20
0.75A.
0.50mm / 1.00mm Vias =
with 17um /=20
0.5oz copper weight, the maximum safety current is=20
0.95A.
0.50mm / 1.00mm =
Vias with=20
25um / 1.0oz copper weight, the maximum safety current is =
1.25A.
For other size or type vias, the current capacity can be estimated by =
equivalent trace capacity, where the trace width can be calculated =
by:=20
diameter*3.14*0.6.
For example, a 0.5mm via is =
effectively a=20
0.95mm width trace on the current carrying=20
capacity.
Thermal vias:
1. Increase plating thickness of the vias where possible to keep =
the=20
thermal resistance minimum.
2. Increasing the pad size of =
the vias=20
is an inexpensive way to improve the thermal spreading =
capacity.
3.=20
Placing multiple small vias evenly at high power dissipation area can =
improve=20
the overall thermal transfer ability comparing with one big =
via.
4.=20
Vias may become filled with the solder during reflow process, this will =
result=20
in less effectively of heat spreading.
5. Making solid =
vias,=20
which thermally conductive material filled into them, can get lower =
thermal=20
resistance. However, this adds an additional
step in =
PCB=20
production so extra cost will be applied.
6. Buried/blind =
vias have=20
higher thermal resistance comparing with the same dimension through =
hole=20
vias.
Other general rules
1. Blind/buried vias are smaller and act less as a discontinuity =
in HDI=20
design. However, the typical PCB manufacturing cost for using =
=20
blind/buried via technologies is 12% higher comparing with =
the same=20
configuration PCBs which only using the normal
through =
hole=20
Vias ( based on Quick=E2=80=90teck 2012 PCB cost analysis=20
report).
2. Place power/ground via =
near=20
power supply pins of IC, so get the power supply path short.
3. Add ground vias nearby the area where high speed signal changes =
layer.=20
This allows the return current flow near to the signal current =
flow,=20
adding positive impact on EMI and signal=20
integrity.
4. Via=E2=80=90in=E2=80=90pad design is better =
thermally than normal pad, but=20
it could be the reason of pseudo soldering in the reflow soldering=20
process.
5. For BGA and =C2=B5BGA solder joints, it is suggested to use filled =
via if=20
Via=E2=80=90in=E2=80=90pad design have to be =
accomplished.
6. High density vias can=20
negatively affect the PCB mechanical performance. PCB twist/wrap =
check is=20
recommended on this area.
Comments
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